The present invention relates to optimizing designs in scalable converter systems and more particularly to keeping a system loop gain unchanged while one converter in a scalable converter system is turned on while other converters are not.
In a multi-phase converter, for example, a multi-phase buck converter illustrated in FIG. 1, a plurality of buck converters are provided each having their output inductors LN coupled to the output node VOUT. In the application shown, each buck converter is controlled by a control IC 10 and may be operated such that a control switch of each buck converter switching stage is turned on at a different time than the other phases. In this way, each phase sequentially provides power to the load, reducing ripple and reducing the size of the output capacitance.
As shown, each phase IC 30 controls a buck converter comprising a switching stage of two transistors Q1 and Q2 and an output inductor LN. Transistor Q1 is the control switch and transistor Q2 is the synchronous switch. A control IC 10 provides a clock signal CLKOUT, to each of the phase ICs 30 at the input CLKIN. Additional phases or phase ICs 30 can be employed depending upon the load requirements in which case the signal lines would extend to the additional phase ICs.
As shown in FIG. 1, clock signal CLKIN is provided to each phase IC 30. In addition, a reduced frequency signal PSHIN is provided to the first phase IC 30a. The signal PSHIN is the clock signal which sets the PWM frequency of the phase IC 30a. The first phase IC 30a provides a signal PHSOUT to the PHSIN input of the next phase IC 30b as a delayed clock signal PHSIN. If there are further phase ICs, then IC 30b will provide a delayed clock signal to the next phase IC and so on.
In FIG. 1, each phase IC has a ramp generator implemented by allowing a charge to develop across a capacitor C for a period of time determined by a circuit including an amplifier A and a share adjust error amplifier B which seeks to maintain equal output currents from each of the phases. The ramp signal across capacitor C is fed as one input to PWM comparator P and another input is provided from the converter's error amplifier 9 (line EAIN). The PWM comparator compares the ramp level with the error amplifier input EAIN and produces an output PWM signal (PWM) which is fed to a latch L and then through gating/drive circuitry as the two drive signals GATEH and GATEL for driving the converter switches Q1 and Q2.
Converters, in such scalable converter application systems, are normally turned on sequentially with a fixed phase shift to pursue the best ripple current cancellation in both input and output sides. These converters form a closed system loop and are turned on sequentially by a shared clock signal, as described. In some applications, the number of phases times the duty ratio may be larger than 1. Some times, one converter may be turned on while other converters are not. In these cases, the gain of the system loop changes. To accommodate these cases, the system loop can not be optimized to pursue cost effective solutions.